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| never stop thinking. automotive and industrial system basis chip tle 6263 integrated ls can, ldo and hs switch final datasheet, version 2.08, 2004-06-07
p-dso-28-18 enhanced power can-ldo-asic tle 6263 version 2.08 2 2004-06-07 final datasheet 1features ? standard fault tolerant differential can-transceiver ? bus failure management ? low power mode management ? receive only mode for can ? can data transmission rate up to 125 kbaud ? low-dropout voltage 5v regulator ? high side switch ? 2 wake-up inputs ? power on and under-voltage reset generator ? window watchdog ? fail-safe output ? early warning feature (v cc warning) ? sense comparator input (v int warning) ? standard 8 bit spi-interface ? flash program mode ? wide input voltage range ? wide temperature range ? enhanced power p-dso-package 2 description the tle 6263 is a monolithic integrated circuit in an enhanced power p-dso-28-18 package. the ic is optimized for use in advanced automotive electronic control units for body and convenience applications. to support this applications the tle 6263 covers the main smart power functions such as failure tolerant low speed can-transceiver for differential mode data transmission, low dropout voltage regulator (ldo) for internal and external 5v supply as well as a spi (serial peripheral interface) to control and monitor the ic. further there are integrated additional features like a high side switch that can be used e.g. for cyclic supply of an external wake-up circuitry, two wake-up inputs, a window watchdog circuit with fail safe output as well as a reset and early warning feature. the ic is designed to withstand the severe conditions of automotive applications. type ordering code package tle 6263 g q67007-a9465 p-dso-28-18 final datasheet tle 6263 version 2.08 3 2004-06-07 3 pin configuration (top view) figure 1: pin configuration tle 6263 g (top view) p-dso-28-6 (enhanced power package) 8 9 gnd gnd gnd 20 21 gnd 10 11 12 v s si 19 18 17 16 15 int 13 14 v cc v ci fso ouths rxd 3 4 5 1 2 24 wk2 txd wk1 canh ro canl 26 25 28 27 rtl 6 7 gnd gnd gnd 22 23 gnd csn clk do rth di final datasheet tle 6263 version 2.08 4 2004-06-07 4 pin definitions and functions pin no. symbol function 1txd transmit data input; integrated pull up; low: bus becomes dominant, high: bus becomes recessive 2rxd receive data output; push-pull output; low: bus becomes dominant, high: bus becomes recessive 3ro reset output ; open drain output, integrated pull up, active low 4 wk2 wake-up input 2; for detection of external wake-up events, edge sensitive, in sleep mode monitored by cyclic sense feature when selected; weak pull up (2a) to avoid unwanted wake ups 5 wk1 wake-up input 1; for detection of external wake-up events, edge sensitive, in sleep mode monitored by cyclic sense feature when selected; weak pull up (2a) to avoid unwanted weak ups 6, 7, 8, 9, 20, 21, 22, 23 gnd ground; to reduce thermal resistance place cooling areas on pcb close to this pins. 10 do spi data output ; this tri-state output transfers diagnosis data to the control device. serial data transfered from do is a 8 bit diagnosis word with the least significant bit (lsb) transmitted first. the output will remain 3-stated unless the device is selected by a low on chip-select-not (csn). do will accept data on the rising edge of clk-signal; see table 4, 5, 6 for diagnosis protocol 11 clk spi clock input ; clocks the shiftregister; clk has a pull down input, active high, and requires cmos logic level inputs 12 csn spi chip select not input ; csn is a pull up input, active low, serial communication is enabled by pulling the csn terminal low; csn input should only be transitioned when clk is low; csn has an internal active pull up and requires cmos logic level inputs 13 di spi data input ; receives serial data from the control device; serial data transmitted to di is a 8 bit control word with the least significant bit (lsb) being transferred first: the input has a pull down input, active high, and requires cmos logic level inputs; di will accept data on the falling edge of clk-signal; see table 3 for input data protocol 14 ouths high side switch output; controlled via spi, in sleep mode controlled by internal cyclic sense function when selected final datasheet tle 6263 version 2.08 5 2004-06-07 15 v s power supply input ; block to gnd directly at the ic with ceramic capacitor 16 si sense comparator input; for monitoring of external voltages, to program the detection level connect external voltage divider 17 fso fail safe output; to supervise and control critical applications, high when watchdog is correctly served, low at any reset condition, open drain output, internal pull up, active low 18 v ci internal voltage supply ; for stabilization of internal power supply, block to gnd with an external capacitor c vi 100 nf 19 v cc voltage regulator output; for 5v supply, to stabilize block to gnd with an external capacitor c q 100 nf 24 canl can-l bus line; low in dominant state 25 rtl canl-termination output; connect to canl bus line via termination resistor 26 canh can-h bus line; high in dominant state 27 rth canh-termination input; connect to canh bus line via termination resistor 28 int interrupt output; to monitor wake-up events or valid sense input condition; integrated pull up resistor; active low 4 pin definitions and functions (cont?d) pin no. symbol function final datasheet tle 6263 version 2.08 6 2004-06-07 5 functional block diagram figure 2: tle 6263 g functional bloc diagram ca n standby / sleep control dr iv er rec eiv er ca n fail detec t filter h output stage l output stage band gap - + res et generator + watchdog ca nh rth ca nl rtl v bat ro v cc rx d txd gnd spi do di clk csn wk1 charge pump fail management temp pr o t e c t time bas e ouths dr iv e + protection early warning / v s supervisor int si fso wk2 v ci input stage vcc vcc vcc vcc vcc vcc vcc vcc vcc vs final datasheet tle 6263 version 2.08 7 2004-06-07 6 circuit description the tle 6263 is a monolithic ic, which incorporates a failure tolerant low speed can- transceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5v supply as well as a spi (serial peripheral interface) to control and monitor the ic. further there are integrated a high side switch, two wake-up inputs, a window watchdog circuit with fail safe output as well as a reset circuit and early warning function. figure 2 shows a schematic block diagram of the tle 6263. table 1 shows the status of the different chip features during the four main operation modes. 1) at low v cc output current only active when watchdog undercurrent function is not activated 2) can only be monitored in v bat -stand-by mode via spi 3) no wake-up interrupt generated, logic level status monitored via spi 4) only active when selected via spi 5) if watchdog under-current function active, than fso = low table 1: truth table of the tle 6263 feature normal mode receive-only mode v bat stand-by mode sleep mode v cc on on on off reset on on on off watchdog on on on 1) off fail safe output on on on 5) off v int -fail 2) on on on on sense input on on on off wake-up 1 / 2 on 3) on 3) on on hs-switch 4) on on on off hs-cyclic-sense 4) off off on on spi on on on off can transmit on off off off can receive on on off off rtl output switched to vcc switched to vcc switched to vs switched to vs rxd output l = bus dominant; h = bus recessive l = bus dominant; h = bus recessive active low wake-up interrupt low int output active low early warning active low early warning for v int and v cc active low early warning low final datasheet tle 6263 version 2.08 8 2004-06-07 6.1 operation modes the tle 6263 offers four different operation modes that are controlled via the spi interface (nstb= spi input bit3, ent=spi input bit2): the normal operation mode , the receive-only mode , the v bat stand-by mode and the sleep operation mode . please see the state diagram ( figure 3 ). normal and receive only mode in the normal operation mode both is possible, receiving and transmitting of messages, in the receive-only mode (rxd-only mode) the output stages are disabled which doesn?t allow the can controller to send a message to the bus. in the state diagram ( figure 3 ), v cc is the status of the voltage regulator. figure 3: state diagram v bat stand-by mode and sleep mode in the v bat stand-by mode and sleep mode the rtl output voltage is switched to v s . both modes are low power modes. in the sleep mode the whole application is switched spi input bits: ibit2 = ent ibit3 = nstb hs cyclic sense nstb off v cc ent 01 hs switch = on v bat stand-by nstb on v cc ent 00 rxd = low if a wake up occured by wk1, wk2 or can message nstb on v cc ent 10 rxd-only start up power up 2) nstb 2) ent 0 1 wake up = transition on wk1 or wk 2 for t > t wu or can message 2) nstb 0 2) nstb ent or v cc 0 0 v rt 2) nstb or v cc 0 v rt normal mode nstb on v cc ent 11 sleep nstb off v cc ent 01 hs switch = off 1) automatic repeated transition only if hs cycl sense feature is selected by spi ibit 4 2) nstb and ent are both spi input bits (ibits) 1) after 64ms 1) after 500s sleep mode power down 2) ent 0 2) ent 1 2) ent 1 2) nstb ent 1 1 2) nstb 1 hs cyclic sense nstb on v cc ent 01 hs switch = on 1) after 64ms 1) after 500s v bat stand-by mode final datasheet tle 6263 version 2.08 9 2004-06-07 off by disabling the voltage regulator. that allows the total current consumption to drop down to less than 100 a. when a reset occurs, due to false watchdog triggering, the TLE6263 automatically switches from normal mode or receive-only mode respectively, to the v bat stand-by mode. if a watchdog reset occurs in the v bat stand-by mode the ic remains in this mode. in sleep mode a wake-up at any of the wake-up inputs as well as via the bus lines (canh or canl) automatically sets the tle 6263 in v bat stand-by mode. in the v bat stand-by mode a wake-up is monitored by setting the output rxd low. this feature works as a flag, to indicate a wake event to the microcontroller. to send and to receive messages, the can-transceiver has to be set to normal operation mode by the microcontroller. in case the ic shall directly be set back to sleep mode after a wake-up, an internal wake- flip-flop has to be reseted via the spi. therefore ibit1 has to be set high and then low again by a second spi transmission. a transition from the v bat stand-by mode to the normal mode or receive-only mode respectively, automatically resets the wake-flip-flop. 6.2 low dropout voltage regulator the integrated low dropout voltage regulator is able to drive the internal loads (e.g. can-circuit) as well as external 5v loads. its output voltage tolerance is better than 2%. the maximum output current is limited to 110 ma. an external reverse current protection is recommended at the pin vs to prevent the output capacitor from being discharged by negative transients or low input voltage. stability of the output voltage is guaranteed for output capacitors c q 100 nf, nevertheless it is recommended to use capacitors c q 10 f to buffer the output voltage and therefore improve the reset behavior at input voltage transients. to stabilize the internal supply a capacitor c vi 100 nf directly connected to the pin v ci is required. 6.3 can transceiver the tle 6263 is optimized for low speed data transmission up to 125 kbaud in automotive applications. figure 4 shows the principle configuration of a can network.normally a differential signal is transmitted and received respectively. when a bus wiring failure (see table 2 ) is detected the device automatically switches to a dedicated canh or canl single-wire mode to maintain the communication if necessary. further a receive-only mode is implemented that allows a separate can node diagnosis. during normal and rxd-only mode, rtl is switched to v cc and rth to gnd. during v bat stand-by and the cyclic wake mode, rtl is switched to v s and rth to gnd. final datasheet tle 6263 version 2.08 10 2004-06-07 figure 4: can network example receive-only mode the receive only mode is designed for a special test procedure to check the bus connections. figure 5 shows a network consisting of 5 nodes. if the connection between node 1 and node 3 shall be tested, the nodes 2,4 and 5 are switched into receive only mode. node 1 and node 3 are in normal mode. if node 1 sends a message, node 3 is the only node which can acknowledge the message, the other nodes can only listen but cannot send an acknowledge bit. if node 1 receives the acknowledge bit from node 3, the connection is ok. figure 5: testing the bus connection in receive-only mode controller 1 rxd1 bus line transceiver1 txd1 controller 2 rxd2 transceiver2 txd2 1 2 5 4 3 final datasheet tle 6263 version 2.08 11 2004-06-07 electromagnetic emmision (eme) to reduce radiated electromagnetic emission (eme), the dynamic slopes of the canl and canh signals are both limited and symmetric. this allows the use of an unshielded twisted or parallel pair of wires for the bus. during single-wire transmission (one of the bus lines is affected by a bus line failure) the eme performance of the system is degraded from the differential mode. 6.4 bus failure management there are 9 different can bus wiring failures defined by the iso 11519-2/iso 11898-3 standard. these failures are devided into 7 failure groups (see table 2 ). the difference between iso11898-3 and iso 11519-2 is also shown in table 2 . when a bus wiring failure is detected the device automatically switches to a dedicated canh or canl single-wire mode to maintain the communication if necessary. therefore it is equipped with one differential receiver and four single ended comparators (two for each bus line). to avoid false triggering by external rf influences, the single wire modes are activated after a certain delay time. as soon as the bus failure disappears the transceiver switches back to differential mode after another time delay. the differential receiver threshold is set to typ. -2.5v. this ensures correct reception in the normal operation mode as well as in the failure cases 1, 2, 3a(6a) and 4(5) with a noise margin as high as possible. when one of the bus failures 3(6), 5(4), 6(3), 6a(3a), and 7 is detected, the defective bus wire is disabled by switching off the affected bus termination and output stage. the failure cases in brackets() are the failure cases according to iso 11898-3. simultaneously the multiplexing output of the receiver circuit is switched to the unaffected single ended comparator the bus failures are monitored via the diagnosis protocoll of the spi. a general indication of a can failure during normal mode at canh or canl is reported by obit 4 and 5. it is also possible to distinguish 6 can bus failures or failure groups on the spi output bits 3 to 7 in the rxonly mode(see table 2 and 5 ). the failures are reported until transmission of the next can word begins. in case the transmission data input txd is permanently dominant, both, the canh and canl transmitting stage are disabled after a certain delay time t txd . this is necessary to prevent the bus from being blocked by a defective protocol unit or short to gnd at the txd input. in order to protect the transceiver output stages from being damaged by shorts on the bus lines, current limiting circuits are integrated. the canl and canh output stage respectively are protected by an additional temperature sensor, that disables them as soon as the junction temperature exceeds the maximum value. in the temperature shut- down condition of the can output stages receiving messages from the bus lines is still possible. final datasheet tle 6263 version 2.08 12 2004-06-07 table 2: can bus line failure cases 6.5 spi (serial peripheral interface) the 8-bit wide programming word (input word, see table 3 ) is read in via the data input di, and this is synchronized with the clock input clk supplied by the c. the diagnostic information depends on the operation mode. the internal latches for the v bat -stand-by diagnosis are reseted when leaving this mode. table 3, input data protocol table 4, diagnosis data protocol all modes normal mode failure # failure description according to iso 11898-3 failure description according to 11519-2 1 canh line interrupted canl line interrupted 2 canl line interrupted canh line interrupted 3 canh shorted to vbat canl shorted to vbat 3a canh shorted to vcc canl shorted to vcc 4 canl shorted to gnd canh shorted to gnd 5 canh shorted to gnd canl shorted to gnd 6 canl shorted to vbat canh shorted to vbat 6a canl shorted to vcc canh shorted to vcc 7 canl shorted to canh canl shorted to canh ibit obit 7 watchdog undercurrent control 7 hs uv / temp-shut down 6set v int -fail + v cc fail flag 6hs overcurrent 5 ouths on 5 canl bus fail 4 ouths cyclic sense 4 canh bus fail 3 not standby 3 wk2 logic level 2 enable transmit 2 wk1 logic level 1 reset internal wk-ff 1 window watchdog reset 0 watchdog trigger 0 temperature prewarning h= on l= off h= on l= off final datasheet tle 6263 version 2.08 13 2004-06-07 the transmission cycle begins when the TLE6263 is selected by the chip select not input csn (h to l). after the csn input returns from l to h, the word that has been read in becomes the new control word. the do output switches to tri-state status at this point, thereby releasing the do bus circuit for other uses. for details of the spi timing please refer to figure 6 to 9 . table 5, diagnosis data protocol table 6, diagnosis data protocol rxd-only mode v bat -stand-by mode 6.6 window watchdog, reset when the input voltage exceeds the reset threshold voltage the reset output ro is switched high after a delay time of typ. 8ms. this is necessary for a defined start of the microcontroller when the application is switched on. as soon as an under-voltage condition of the output voltage (v cc < v rt ) appears, the reset output ro is switched low again (power on and under-voltage reset). the low signal is guaranteed down to an output voltage v q 1v. please refer to figure 13 , reset timing diagram . in sleep operation mode, the watchdog circuit is automatically disabled. long open window after the above described delayed reset (low to high transition of ro) the window watchdog circuit is started by opening a long open window of typ. 65ms. the long open window allows the microcontroller to run his set-up and then to trigger the watchdog via the spi, refer to figure 11 , watchdog timeout definitions . within the long open window obit obit 7 can failure 5(4) and 7 7 v cc not-fail 6 can failure 6 (3) 6 v int not-fail 5 can failure 6a (3a) 5 wk1/2 initialization fail 4 can failure 2(1) and 4(5) 4 wake via can bus lines 3 can failure 3(6) 3 wk2 voltage level 2 can failure 1(2) and 3a(6a) 2 wk1 voltage level 1 window watchdog reset 1 window watchdog reset 0 temperature prewarning 0 temperature prewarning h= on l= off ()... values in brackets according to iso11898-3 see table 2 h= on l= off final datasheet tle 6263 version 2.08 14 2004-06-07 period a watchdog trigger is detected as a ?rising edge? by sampling a high on the ibit 0. the trigger is accepted when the csn input becomes high after the transmission of the spi word. after each reset as well as after a power on condition the default value of ibit 0 is low. closed and open window a correct watchdog trigger results in starting the window watchdog by opening a closed window of typ. 6 ms followed by a open window of typ. 10 ms. from now on the microcontroller has to service the watchdog trigger by inverting the ibit 0 alternating . the ?negative? or ?positive? edge has to meet the open window time. a correct watchdog service immediately results in starting the next closed window. please refer to figure 12 , watchdog timing diagram. watchdog reset should the trigger signal not meet the open window a watchdog reset is created by setting the reset output ro low for a period of typ. 2 ms. then the watchdog starts again by opening a long open window. in addition, the spi obit 1 (diagnosis bit 1) is set high until the next successful watchdog trigger to monitor a watchdog reset. obit1 is also high until the watchdog is correctly triggered after power-up / start-up. for fail safe reasons the TLE6263 is automatically switched in vbat-stand-by mode if a watchdog trigger failure occurs. so the power consumption can be minimized in case of a permanent faulty microcontroller. in case of either an undervoltage reset or a watchdog reset all spi input registers (ibit 0 to ibit 7) are set low. undercurrent disabling function to avoid cyclic wake-up?s of the microcontroller due to missing watchdog pulses when the microcontroller is in a low power mode, an automatic undercurrent disabling function of the watchdog circuit can be selected for the tle 6263 v bat -stand-by mode. for activation of this feature, the v cc output current in the v bat -stand-by mode has to be less than the undercurrent threshold (i cc < i ccwd ) and in addition the spi ibit 7 has to be set high. when the microcontroller returns back to normal mode or the output current becomes higher than i cc > i ccwd the watchdog circuit is enabled again. a long open window is started then, to ensure a simple synchronization of the watchdog timing to the watchdog services of the microcontroller. 6.7 flash program mode to disable the watchdog feature a flash program mode is available. this mode is selected by applying a voltage of 6.8v < v int < 7.2v at pin int. this is useful e.g. if the flash-memory of the micro has to be programmed and therefore a regular watchdog triggering is not possible. if the spi is required in the flash program mode to change e.g. the mode of the TLE6263 the first input telegram has to be ?00000000?. final datasheet tle 6263 version 2.08 15 2004-06-07 6.8 fail safe feature the output fso becomes high when the watchdog is correctly serviced by the microcontroller for the fourth time . as soon as either an under-voltage reset or watchdog reset occurs, it is set low again. this feature is very useful to control critical applications independent of the due function of the microcontroller e.g. to disable the power supply in case of a microcontroller failure. 6.9 sense comparator (pin si) and v int -fail the sense comparator (early warning function) compares a voltage defined by the user to an internal reference voltage. therefore the voltage to be supervised has to be scaled down by an external voltage divider in order to compare it to the internal sense threshold v sith . this feature can be used e.g. to supervise the battery voltage in front of the reverse protection diode. the microcontroller is given a pre-warning before an under-voltage reset due to low input voltage occurs. the pre-warning is flagged by setting the interrupt output int low in normal mode, receive only mode and v bat -stand-by mode. in sleep operation mode the sense function is inactive. calculation of the voltage divider can be easily done since the sense input current can be neglected. an internal blanking time prevents from false triggering due to line transients. further improvement is possible by the use of an external ceramic capacitor switched between si and gnd (see application diagram figure 15 ). 6.10 v int - and v cc -fail flag to activate the v int supervisor feature the spi ibit 6 has to be set high to set an internal flip-flop. this automatically sets the v bat -stand-by obit 6 high, too. should the internal supply voltage become lower than the internal threshold v vint,th (typ. 2.5v) the not v int -fail bit becomes low to indicate the low voltage condition. all spi input registers are set low due to a low voltage condition of the internal supply voltage. like the wake-up diagnosis the v int -fail diagnosis can only be monitored in the v bat - stand-by mode. the v int -fail feature can also be used to give an indication when the ecu has been changed and therefore a pre-setting routine of the microcontroller has to be started. further to the reset threshold there is another supervisor threshold implemented, to monitor the output voltage v cc . this threshold is called v vcc,th (typ. 2.5v). the not v cc -fail feature is monitored via obit 7 in the v bat -stand-by mode and set, like the not v int -fail flag, via ibit 6 (so both fail features are activated with the ibit 6 but monitored via obit 6 and obit 7 during v bat -stand-by). in the receive-only mode both fail bits cause the interrupt output int to go low. final datasheet tle 6263 version 2.08 16 2004-06-07 6.11 wake-up inputs wk1, wk2 in addition to a wake-up from sleep mode via the bus lines canh or canl it is also possible to wake-up the TLE6263 from low power mode via the wake-up inputs wk1 and wk2. the wake-up inputs are sensitive to a transition of the voltage level, either from high to low or the other way round . they are active in all operation modes . in the normal mode the current logic level at wk1/2 is monitored via the spi (see table 4 and 6 ). a positive or negative voltage edge at wk1/2 in v bat -stand-by mode or sleep mode immediately results in setting the output rxd low to signal a wake-up . after a wake-up via wk1/2 the transmission of the spi diagnosis word in the v bat -stand-by mode shows the logic level that has caused the wake-up. to get the current voltage levels at wk1/2 in the v bat -stand-by mode the internal wake flip-flop has to be reseted by the ibit1 for each transmission. as long as ibit1 is set high or the internal wake flip-flop is reseted respectively, in the v bat -stand-by mode the rxd output is blocked to signal a new wake- up event via the can-bus or the wake-up inputs. further to the continues sensing at the wake-up inputs a cyclic sense feature is possible. when the ouths cyclic sense feature is selected via the spi ibit 4 the high side switch as well as the wk1/2 inputs are periodically activated by the TLE6263 in the sleep and v bat -stand-by mode. when switching the TLE6263 into sleep mode (cyclic sense feature activated) the voltage level at the wake-inputs is sensed 2 times to initialize the reference voltage. should this initialisation fail (2 samples are unequal) the device is automatically set in v bat -stand-by mode and the initialisation error is shown on the obit 5. to enter the sleep mode now directly from the v bat -stand-by mode, the internal wake flip-flop has to be reseted by the ibit 1. 6.12 interrupt output int like the reset output, the interrupt output is a low active output. it is used to monitor low voltage conditions at the sense input in normal mode and stand-by mode (see table 8 ). in the receive-only mode the v int -fail flag and v cc supervisor are monitored. 6.13 high side switch the high side output ouths is able to switch loads up to 150 ma. its on-resistance is 1.0 ? typ. @ 25c. this switch is controlled via the spi input bits 4 and 5. in normal mode, receive-only mode and v bat -stand-by mode the high side output is switched on and off, respectively via the spi input bit 5. to supply external wake-up circuits in sleep mode and v bat -stand-by mode the output ouths can be periodically switched on by the TLE6263 itself. in order to activate this cyclic sense feature the spi ibit 4 has to be set high. the auto-timing period then is typ. 65 ms, the on-time is typ. 1 ms. should there be any over-current condition at the switch in the sleep mode (cyclic sense activated) or v bat -stand-by mode a wake-up is flagged final datasheet tle 6263 version 2.08 17 2004-06-07 via the rxd output. the over-current condition is monitored on the spi obit 6 in normal operation mode. the spi obit 0 flags a thermal pre-warning of the high side switch. by this the microcontroller is able to reduce the power dissipation of the TLE6263 by switching off functions of minor priority until the temperature threshold of the thermal shutdown is reached. further ouths is protected against short circuit and overload. as soon as the under-voltage condition of the supply voltage is met (v s < v uvoff ), the switch is automatically disabled by the under-voltage lockout circuit. moreover the switch is automatically disabled when a reset or watchdog reset occurs. 6.14 hints for unused pins si: connect to v s ouths: leave open wk1/2: connect to v s or leave open int: leave open ro: leave open fso: leave open si: switch to vs final datasheet tle 6263 version 2.08 18 2004-06-07 7 electrical characteristics 7.1 absolute maximum ratings parameter symbol limit values unit remarks min. max. voltages supply voltage v s -0.3 28 v supply voltage v s -0.3 40 v t p < 0.5s; t p /t < 0.1 regulator output voltage v cc -0.3 5.5 v can bus voltage (canh, canl) v canh/l -20 28 v can bus voltage (canh, canl) v canh/l -40 40 v v s >0 v t p < 0.5s; t p /t < 0.1 logic input voltages (di, clk, csn, osc, txd) v i -0.3 v cc +0.3 v 0 v < v s < 24 v 0 v < v cc < 5.5 v logic output voltage (do, ro, int, rxd, fso) v dri,rd -0.3 v cc +0.3 v 0 v < v s < 24 v 0 v < v cc < 5.5 v termination input voltage (rth, rtl) v tl /th -0.3 v s +0.3 v 0 v < v s < 24 v 0 v < v cc < 5.5 v input voltages at wk1/2 and si v wk/si -40 40 v electrostatic discharge voltage at pin canh, canl, gnd, v s v esd -3 3 kv human body model, c = 100 pf, r = 1.5 k ? electrostatic discharge voltage at any other pin v esd -1 1 kv human body model, c = 100 pf, r = 1.5 k ? currents output current; vcc i cc ??a 1) internally limited output current; ouths i outh1 1) 0.2 a 1) internally limited note 1): not subject to production test - specified by design final datasheet tle 6263 version 2.08 19 2004-06-07 note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. temperatures junction temperature t j ? 40 150 c ? storage temperature t stg ? 50 150 c ? 7.1 absolute maximum ratings (cont?d) parameter symbol limit values unit remarks min. max. final datasheet tle 6263 version 2.08 20 2004-06-07 7.2 operating range parameter symbol limit values unit remarks min. max. supply voltage v s v uv off 20 v after v s rising above v uv on supply voltage v s v uv off 40 v thermally limited supply voltage slew rate d v s / d t ?0.5 5 v/ s logic input voltage (di, clk, csn, txd) v i ? 0.3 v cc v output capacitor c cc 100 nf output capacitor c vi 100 460 nf spi clock frequency f clk 1.5 mhz junction temperature t j ? 40 150 c thermal resistances junction pin r thj-pin ?25k/w junction ambient r thj-a ?65k/w note: calculation of the junction temperature t j = t amb + p x r thj-a final datasheet tle 6263 version 2.08 21 2004-06-07 7.3 electrical characteristics v s = 13.5 v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j <150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. quiescent current pin v s current consumption i q = i s - i cc i q ?5.510ma normal mode; i cc =30ma; txd recessive current consumption i q = i s - i cc i q ?810ma normal mode; i cc =30ma; txd dominant current consumption i q = i s - i cc i q ? 300 400 a stand-by mode; t j =25c; i cc =1ma; ibit 7 = h current consumption i q ?5080 a sleep mode; t j =25c; spi ibit 4 = l; v cc = v cci = 0 v current consumption i q 3ma ouths active; spi ibit 4 = h; sleep mode; v cc = v cci = 0 v voltage regulator; pin v cc output voltage v cc 4.95.05.1v 0.1 ma< i cc <100ma 6v final datasheet tle 6263 version 2.08 23 2004-06-07 watchdog undercurrent disable hysteresis i ccwdhys 0.5 ma watchdog undercurrent reaction time t lhr 8s t j =25c fail safe output; pin fso watchdog edge count difference to set high n fs 4v fail safe low output voltage v fs 0.2 0.4 v i fso = 1ma for v cc = v rt or i fso = 200 a for v cc 1v fail safe high output voltage v fs 4.0 v cc + 0.1 v i fso = -1ma for v cc v rt sense input (early warning) si, v int -fail, interrupt output int sense in threshold voltage v si,th 2.12.32.5v v si decreasing until int transition to low sense in threshold hysteresis v si,hys 200 mv sense input current i si 0.1 a v si 0v sense reaction time t s,r 51020s v s < v s,th to int = low interrupt out high voltage v inthigh 0.7 x v cc ? v cc v i 0 = ? 20 a interrupt out low voltage v intlow 0?0.9v i 0 = 1.25 ma interrupt pull up current i int 20 150 500 a v int = 0v v cc -fail threshold voltage v vcc,th 2.32.83.1v v cc -fail reaction time t vcc,r 5s v cc < v vcc,th to obit 6 = low; v bat - stand-by mode v int -fail threshold voltage v vint,th 1.53.24.3v proportional to v s 7.3 electrical characteristics (cont?d) v s = 13.5 v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j <150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 24 2004-06-07 wake-up inputs wk1 / wk2 wake-up threshold voltage v wuth 234v sleep mode; vbat- stand-by mode minimum time for wake-up t wu 10 15 32 s sleep mode; vbat- stand-by mode input current i wk -2 a v wk = 0 v high side output ouths; (controlled by bit 4 and bit 5 of spi input word) static drain-source on-resistance; i outh3 = ?0.15a r dson hs ?1.01.5 ? t j = 25 c ?3.0 ? 2.5 3.0 ? 5.2 v v s 9v t j = 25 c ?5.0 ? 5.2 v v s 9v active zener voltage v ouths ?2 v i ouths = ? 0.15 a clamp diode forward voltage v ouths 1v i ouths = 0.15 a leakage current i qlhs ?4 a v ouths = 0 v switch on delay time t donhs 20 s csn high to ouths switch off delay time t doffhs 20 s csn high to ouths overcurrent shutdown threshold i sdhs ?0.8 ?0.3 ?0.2 a ? shutdown delay time t dsdhs 10 35 50 s current limit i oclhs ?1.2 ?0.6 ?0.3 a uv-switch-on voltage v uv on ?5.26.0v v s increasing uv-switch-off voltage v uv off 4.54.75.2v v s decreasing uv-on/off-hysteresis v uv hy ?0.5?v v uv on ? v uv off cyclic sense period (128 cyl.) t p cs 38 65 92 ms sleep mode spi-bit 4 = h, 7.3 electrical characteristics (cont?d) v s =13.5v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j < 150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 25 2004-06-07 cyclic sense period (128 cyl.) t p cs 55 65 80 ms vbat-stand-by mode; spi-bit 4 = h; watchdog under- current feature active cyclic sense on time (1 cyl.) t cs on 0.5 ms can-transceiver receiver output r d high level output voltage v oh v cc -0.9 v cc v i 0 = -250 a low level output voltage v ol 00.9v i 0 = 1.25 ma transmission input t d high level input voltage threshold v ih 0.52 v cc 0.7 v cc v low level input voltage threshold v il 0.3 v cc 0.48 v cc v high level input current i ih -150 -30 -10 a v i = 4 v low level input current i il -600 -300 -40 a v i = 1 v bus lines canl, canh differential receiver recessive-to-dominant threshold voltage v drxdrd -2.8 -2.5 -2.2 v differential receiver dominant-to-recessive threshold voltage v drxddr -3.1 -2.9 -2.5 v canh recessive output voltage v canhr 0.10.20.3v txd = v cc ; r rth < 4 k ? 7.3 electrical characteristics (cont?d) v s = 13.5 v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j <150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 26 2004-06-07 canl recessive output voltage v canlr v cc -0.2 v txd = v cc ; r rtl < 4 k ? canh dominant output voltage v canhd v cc -1.4 v cc -1.0 v cc v txd = 0 v; i canh = ? 40 ma canl dominant output voltage v canld 1.0 1.4 v txd = 0 v; i canl = 40 ma canh output current i canh -110 -80 -50 ma v canh = 0 v; txd = 0 v -5 5 a sleep mode; v canh = 12 v canl output current i canl 50 80 110 ma v canl = 5 v; txd = 0 v -5 5 a sleep mode; v canl = 0 v voltage detection threshold for short-circuit to battery voltage on canh and canl v det(th) 6.57.38.0v canh wake-up voltage threshold v h,wk 1.21.92.7v low power modes canl wake-up voltage threshold v l,wk 2.23.13.9v low power modes canh single-ended receiver threshold v canh 1.62.12.6v failure cases 3, 5, 7 recessive to dominant canl single-ended receiver threshold v canl 2.42.93.4v failure case 6 and 6a recessive to dominant canl leakage current i canll -5 5 a v cc =0v, v s =0v, v canl =13.5v canh leakage current i canhl -5 5 a v cc =0v, v s =0v, v canh =5v 7.3 electrical characteristics (cont?d) v s =13.5v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j < 150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 27 2004-06-07 termination outputs rtl, rth rtl to v cc switch-on resistance r rtl 40 95 ? i o =?10 ma; rtl to bat switch series resistance r ortl 51530k ? v bat -stand-by or sleep mode rth to ground switch-on resistance r rth 40 95 ? i o = 10 ma; rth output voltage v orth 0.7 1.0 v i o = 1 ma; sleep mode or v bat -stand-by rth pull-down current i rthpd 40 75 120 a failure cases 6 and 6a rtl pull-up current i rtlpu -120 -75 -40 a failure cases 3, 3a, 5 and 7 rth leakage current i rthl -5 5 a v cc =0v, v s =0v, v rth =5v, t j <85c rtl leakage current i rtll -5 5 a v cc =0v, v s =0v v rtl = 13.5 v, t j <85c can-transceiver dynamic characteristics canh and canl bus output transition time recessive-to- dominant t rd 0.61.22.1s 10% to 90%; c 1 = 10 nf; c 2 = 0; r 1 = 100 ? canh and canl bus output transition time dominant-to- recessive t dr 0.30.61.3s 10% to 90%; c 1 = 1 nf; c 2 = 0; r 1 = 100 ? minimum dominant time for wake-up on canl or canh t wu(min) 12 20 32 s stand-by modes 7.3 electrical characteristics (cont?d) v s = 13.5 v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j <150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 28 2004-06-07 failure cases 3 and 6 detection time t fail 25 45 80 s failure case 6a detection time 2.0 4.8 8.0 ms failure cases 5 and 7 detection time 1.02.04.0ms failure cases 5, 6, 6a and 7 recovery time 25 45 80 ms failure cases 3 recovery time 250 500 750 s failure cases 5 and 7 detection time t fail 0.41.02.4ms stand-by modes failure cases 6 and 6a detection time 0.84.08.0ms stand-by modes failure cases 5, 6, 6a and 7 recovery time 0.41.02.4ms stand-by modes propagation delay txd-to-rxd low (recessive to dominant) t pd(l) ?1.52.1s c 1 = 100 pf; c 2 = 0; r 1 = 100 ? ; no failures and bus failure cases 1, 2, 3a and 4 ?1.72.4s c 1 = c 2 = 3.3 nf; r 1 = 100 ? ; no bus failure and failure cases 1, 2, 3a and 4 ?1.82.5s c 1 100 pf; c 2 = 0; r 1 = 100 ? ; bus failure cases 3, 5, 6, 6a and 7 ?2.02.6s c 1 = c 2 = 3.3 nf; r 1 =100 ? ; bus failure cases 3, 5, 6, 6a and 7 7.3 electrical characteristics (cont?d) v s =13.5v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j < 150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 29 2004-06-07 propagation delay txd-to-rxd high (dominant to recessive) t pd(h) ?1.32.0s c 1 = 100 pf; c 2 = 0; r 1 =100 ? ; no failures and bus failure cases 1, 2, 3a and 4 ?2.53.5s c 1 = c 2 = 3.3 nf; r 1 = 100 ? ; no bus failure and failure cases 1, 2, 3a and 4 ?1.32.1s c 1 100 pf; c 2 = 0; r 1 = 100 ? ; bus failure cases 3, 5, 6, 6a and 7 ?1.72.6s c 1 = c 2 = 3.3 nf; r 1 = 100 ? ; bus failure cases 3, 5, 6, 6a and 7 edge-count difference (falling edge) between canh and canl for failure cases 1, 2, 3a and 4 detection n e ?4?? edge-count difference (rising edge) between canh and canl for failure cases 1, 2, 3a and 4 recovery ?2?? txd permanent dominant disable time t txd 1.32.03.5ms spi-interface logic inputs di, clk and csn h-input voltage threshold v ih ? ? 0.7 x v cc v ? l-input voltage threshold v il 0.3 x v cc ??v ? hysteresis of input voltage v ihy 50 200 500 mv ? pull up current at pin csn i icsn ?100 ?25 ?5 a v csn = 0.7 v cc 7.3 electrical characteristics (cont?d) v s = 13.5 v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j <150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 30 2004-06-07 pull down current at pin di and clk i iclk/di 525100 a v di = 0.2 v cc input capacitance at pin csn, di or clk c i ?1015pf not subject to production test - specified by design logic output do h-output voltage level v doh v cc ? 1.0 v cc ? 0.7 ?v i doh =1 ma l-output voltage level v dol ? 0.2 0.4 v i dol = ? 1.6 ma tri-state leakage current i dolk ? 10 ? 10 a v csn = v cc 0v < v do < v cc tri-state input capacitance c do ?1015pf not subject to production test - specified by design data input timing not subject to production test - specified by design clock period t pclk 1000 ? ? ns ? clock high time t clkh 500 ? ? ns ? clock low time t clkl 500 ? ? ns ? clock low before csn low t bef 500 ? ? ns ? csn setup time t lead 500 ? ? ns ? clk setup time t lag 500 ? ? ns ? clock low after csn high t beh 500 ? ? ns ? di setup time t disu 250 ? ? ns ? di hold time t diho 250 ? ? ns ? input signal rise time at pin di, clk and csn t rin ? ?200ns ? input signal fall time at pin di, clk and csn t fin ? ?200ns ? 7.3 electrical characteristics (cont?d) v s =13.5v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j < 150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 31 2004-06-07 data output timing not subject to production test - specified by design do rise time t rdo ? 50 100 ns c l = 100 pf do fall time t fdo ? 50 100 ns c l = 100 pf do enable time t endo ? ? 250 ns low impedance do disable time t disdo ? ? 250 ns high impedance do valid time t vado ? 100 250 ns v do < 0.1 v cc ; v do > 0.9 v cc ; c l = 100 pf thermal prewarning and shutdown (junction temperatures) not subject to production test - specified by design ouths thermal prewarning on temperature t jpw 120 145 170 c bit 0 of spi diagnosis word ouths thermal prewarning hyst. ? t ?30 ?k ? ouths thermal shutdown temp. t jsd 150 175 200 c ? ouths thermal switch-on temp. t jso 120 ? 170 c ? ouths thermal shutdown hyst. ? t ?30 ?k ? ouths ratio of sd to pw temp. t jsd / t jpw 1.20 ? ? ? vcc thermal shutdown temp. t jsd 155 185 200 c hysteresis 15k (typ.) ouths thermal shutdown temp. t jsd 150 c hysteresis 15k (typ.) 7.3 electrical characteristics (cont?d) v s = 13.5 v; i cc = 1 ma; normal mode; all outputs open; ? 40 c< t j <150 c (max. 125c for can circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. final datasheet tle 6263 version 2.08 32 2004-06-07 8 timing diagrams figure 6: spi-data transfer timing figure 7: spi-input timing di clk c s n do c s n h i g h t o l o w & r i s i n g e d g e o f c l k : d o i s e n a b l e d . s t a t u s i n f o r m a t i o n i s t r a n s - f e r e d t o o u t p u t s h i f t r e g i s t e r csn low to high: data from shift-register is transfered to e.g. hs-switch previous status actual data di: data will be accepted on the falling edge of clk-signal do: state will change on the rising edge of clk-signal time n e w d a t a actual status eg. ouths actual data old data 0 1 0 7 6 5 4 3 2 1 + 1 0 0 7 6 5 4 23 0 + 7 6 5 4 3 2 1 1 01 final datasheet tle 6263 version 2.08 33 2004-06-07 figure 8: turn off/on time figure 9: do valid data delay time and valid time final datasheet tle 6263 version 2.08 34 2004-06-07 figure 10: do enable and disable time figure 11: watchdog time-out definitions closed window 10.0 open window t cwmin t / ms max. 7.2 min. 13.6 t wd t owmax min. 5.1 max. 18.9 save trigger area t cwmax t owmin final datasheet tle 6263 version 2.08 35 2004-06-07 figure 12: watchdog timing diagram figure 13: reset timing diagram t wdr watchdog timer reset normal operation timeout (to long) timeout (to short) normal operation reset out wd trigger ibit 0 t t normal operation t cw t ow t lw t cw t ow t cw +t ow t lw t cw t cw t ow t cw t ow t lw t rd t lw t wdr watchdog timer reset start up start up reset out wd trigger ibit 0 t v cc v rt undervoltage t rd normal operation t t t lw t lw t cw t ow v int-fail t < t rr activation by microcontroller t spi diagnosis bit 6 v int -fail flag in v stb - mode low high t rr t sr t cw final datasheet tle 6263 version 2.08 36 2004-06-07 figure 14: test circuit +vs wk1 canh canl rth rtl di do txd csn ro v cc rxd clk wk2 ouths 13.5 v 22 f int si 100 nf 20 pf c 1 5 v c 1 c 2 gnd fso r 1 r 1 v ci 100 nf final datasheet tle 6263 version 2.08 37 2004-06-07 9 application figure 15: application circuit +v s wk1 v bat gnd canh canl rth rtl can bus di tle 6263 68 f 100 nf gnd p do txd csn ro v cc rxd clk fso ouths 10 k ? 1 k ? 1 k ? 22 f e.g. c505c, c164c int si 100 k ? 160 k ? wk2 v ci 100 nf 26 5 3 4 28 14 16 13 10 11 12 1 2 25 27 24 6 - 9; 20 - 23 18 17 15 19 100 nf *) 10nf *) only for improvement refer to 6.9) final datasheet tle 6263 version 2.08 38 2004-06-07 10 package outlines gps05123 p-dso-28-18 (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm smd = surface mounted device final datasheet tle 6263 version 2.08 39 2004-06-07 published by infineon technologies ag, st.-martin-strasse 53, d-81669 mnchen ? infineon technologies ag 2001 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infi- neon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system . life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. infineon goes for business excellence ?business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.? dr. ulrich schumacher http://www.infineon.com published by infineon technologies ag |
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